This invention relates to the field of integrated circuits packaged in a molded housing. More particularly, this invention relates to a method of suppressing noise (e.g. decoupling) from the voltage to ground distribution circuit in integrated circuit packages such as surface mounted leaded or leadless chip carriers, dual-in-line packages, and quad flat packages.
This application is related to U.S. application Ser. No. 479,075 entitled MOLDED INTEGRATED CIRCUIT PACKAGE INCORPORATING DECOUPLING CAPACITOR invented by Jorge Hernandez, U.S. application Ser. No. 479,095 entitled THIN CAPACITOR FOR MOUNTING UNDER INTEGRATED CIRCUIT PACKAGE invented by Jorge Hernandez and A. B. Feinberg, and U.S. application Ser. No. 479,094 entitled INTEGRATED CIRCUIT PACKAGE HAVING AN INTERNAL CAVITY FOR INCORPORATING DECOUPLING CAPACITOR invented by Jorge Hernandez, all of which have been filed contemporaneously with this application.
It is well known in the field of microelectronics that high frequency operation, particularly the switching of integrated circuits, can result in transient energy being coupled into the power supply circuit. It is also well known that integrated circuits are becoming more dense (more gates per unit area of silicon/or gallium arsenide), more powerful (more watts per unit area of IC chip), and faster with higher clock rate frequencies and with smaller rise times. All of these recent developments make the problem of suppressing noise in the power bus (produced by a large amount of simultaneous gates switching) even more serious than in the past.
Generally, the prevention of the coupling of undesired high frequency noise or interference into the power supply for an integrated circuit is accomplished by connecting a decoupling capacitor between the power and the ground leads of the IC. Conventional methods of decoupling (noise suppression) include the use of decoupling capacitors external to the IC package, such as monolithic multilayer ceramic chip capacitors. One external connection scheme of this type which has been found to be quite successful is to mount a decoupling capacitor underneath an integrated circuit. Such decoupling capacitors are commercially available from Rogers Corporation (assignee of the present application) and are sold under the trademark MICRO Q. Examples of these decoupling capacitors are found in U.S. Pat. Nos. 4,475,143, 4,502,101 and 4,748,537, all of which are assigned to the assignee hereof. U.S. Pat. Nos. 4,626,958, 4,667,267, 4,658,327, 4,734,818, 4,734,819 and 4,853,826 are also assigned to the assignee hereof. These patents disclose decoupling capacitors which are particularly well suited for pin grid array and plastic leaded chip carrier packages.
Still other decoupling connection schemes are known. For example, multilayer capacitor (MLC) chips have been placed on top of PGA ceramic IC packages with interconnections built in from the surface of the PGA package down to the proper places in the internal circuitry of the package. In still some other cases, schemes have been devised to incorporate a MLC chip into a specially configured IC lead frame, but due to production difficulties, this approach has not become widely accepted. Attempts have also been made to build a capacitive layer into a PGA ceramic package (and into a leadless ceramic chip carrier), by using thin layers of alumina or other adequate ceramic dielectric material. Again, this approach has not found wide acceptance.
For a number of years, the users of integrated circuits have been aware of the need to reduce the inductance of the decoupling loop, so that switching noise can be minimized. The best way to accomplish this is by placing the decoupling capacitor as close to the IC chip (silicon or gallium arsenide) as possible. Ideally, the decoupling capacitor should be built in with the IC itself. However, due to materials and processing incompatabilities, this is not possible at the present time.
Accordingly, there continues to be a need for improved connection schemes for decoupling undesired high frequency noise from integrated circuits wherein the inductance within the decoupling loop is reduced to as low a level as possible. A recent attempt at providing an improved connection scheme is disclosed in my aforementioned U.S. application Ser. No. 479,075 entitled "Molded Integrated Circuit Package Incorporating Decoupling Capacitor". In accordance with this co-pending application, a parallel plate-type decoupling capacitor is attached directly to the IC lead frame and thereafter encapsulated within the molded package along with the IC chip resulting in a decoupling scheme which is internal to the molded IC package. The capacitor preferably comprises a thin layer of ceramic dielectric sandwiched between top and bottom conductors. The top conductor may be attached to the die bar of the lead frame using an electrically conductive or non-conductive adhesive. Leads extending from the capacitors are attached to appropriate fingers of the lead frame by welding, soldering or the like to effect strong mechanical and electrical contact. While this decoupling scheme provides many features and advantages relative to prior art decoupling schemes it still nevertheless exhibits a level of inductance which may be undesirable for certain very dense, high speed IC chips.